1. Field of the Invention
This invention relates to an electrostatic protection circuit of a semiconductor device and more particularly to an electrostatic protection circuit of an open drain output circuit and input circuit.
2. Description of the Prior Art
Conventionally, various types of electrostatic protection circuits have been used to protect an output terminal or input terminal of a MOS semiconductor device. For example, in an open drain output circuit having a structure shown in FIG. 5(a), a parasitic diode d1 existing between a drain of an N channel type MOS transistor tr1 and power terminal VSS (0V as substrate potential) is used as a protection circuit. That is, if a high positive surge voltage is applied to an output terminal OUT with respect to a power terminal VSS, the surge current is made to escape to the power terminal VSS through a breakdown of the parasitic diode d1 so as to prevent a destruction of the MOS transistor tr1.
According to a second example shown in FIG. 5(b), in addition to the parasitic diode d1, a MOS transistor tr2 in which its drain is connected to an output terminal, its source is connected to a power terminal VDD and its gate is connected to a power terminal VSS so that it is turned off is provided as the protection circuit. In this case, if a high positive surge voltage is applied to the output terminal with respect to the power terminal VSS, the surge current is made to escape through the same path as shown in FIG. 5(a) and simultaneously the surge current is made to escape to the power terminal VDD through the drain and source of the MOS transistor tr2 causing break down. The surge current flows to the power terminal VSS through a parasitic diode d2 existing between the power terminal VDD and power terminal VSS.
As for the protection circuit for the input terminal, as shown in FIG. 5(c), generally diodes d3, d4 have been disposed.
However, because there is no protection circuit between the power terminal VDD and output terminal in the example shown in FIG. 5(a), electrostatic discharge (ESD) withstanding voltage is low, and therefore a special process is needed to raise this voltage.
In the example shown in FIG. 5(b), although the ESD withstanding voltage can be raised by adding the MOS transistor tr2 between the power terminal VDD and output terminal, it is necessary to increase a size of the MOS transistor tr2 thereby inducing an increase of the circuit size.
In the protection circuit for the input terminal shown in FIG. 5(c), because the diode d4 exists between the input terminal IN and power terminal VDD, an input signal having a higher potential than the power terminal VDD cannot be used. That is, this circuit is not capable of receiving an input signal from a semiconductor device having a different voltage.